1. Field of the Invention
The present invention relates to fabrication methods of semiconductor package structures, and more particularly, to a fabrication method of a semiconductor package structure characterized by high quality of wire bonding but not susceptible to solder bridging.
2. Description of Related Art
In a conventional lead frame based semiconductor package such as a QFN (Quad Flat Non-lead) package, a semiconductor chip is attached and wire-bonded to a lead frame and encapsulated by an encapsulant, and metal portions around the lead frame are exposed from the encapsulant to serve as contact pads for connection with an external device. A semiconductor package structure thus fabricated is advantageously characterized by reduced size, improved electrical performance, and wide application in the industry.
FIG. 1A shows a conventional fabrication method of a semiconductor package structure as disclosed by U.S. Pat. No. 6,143,981, No. 6,424,024, No. 6,414,385, No. 5,942,794, No. 6,420,779, No. 6,399,415 and No. 6,291,274.
Referring to FIG. 1A, a semiconductor chip 11 is disposed on a lead frame 10 and electrically connected to contact pads 101 peripherally provided on the lead frame 10 through bonding wires 12, and an encapsulant 13 is formed on the lead frame 10 to encapsulate the semiconductor chip 11 and the bonding wires 12, thereby allowing the side surfaces and bottom surfaces of the contact pads 101 to be exposed from the encapsulant 13.
FIG. 1B is a side view of the semiconductor package structure 1 of FIG. 1A connected to a circuit board 15. Referring to FIG. 1B, the contact pads 101 are connected to solder pads 151 of the circuit board 15 through a solder material 14. However, since the contact pads are closely arranged and do not protrude from the bottom surface of the semiconductor package structure 1, when the semiconductor package structure 1 is soldered to the circuit board 15, the gap between the contact pads 101 and the solder pads 151 of the circuit board 15 is so small that it is difficult to control the gap. As a result, the reliability of the solder joints is low, the solder joints are easy to crack, and the soldering situation is difficult to check. Due to the small gap between the semiconductor package structure 1 and the circuit board 15, the solder material 14 overflows readily to thereby cause solder bridging.
Further, the semiconductor package structure 1 cannot provide array arranged contact pads and accordingly cannot provide a semiconductor package structure with high density I/O connections.
Accordingly, U.S. Pat. No. 6,498,099, No. 7,049,177, No. 6,238,952, No. 6,700,188 and No. 6,777,265 disclose a fabrication method of a semiconductor package structure, as shown in FIGS. 2A and 2B.
FIG. 2A is a cross-sectional view of a conventional fabrication method of a semiconductor package structure 2 and FIG. 2B is a top view of the semiconductor package structure 2. Referring to FIGS. 2A and 2B, half of the thickness of the lead frame 20 is etched away; a semiconductor chip 21 is disposed on the lead frame 20 and electrically connected to contact pads 201 peripherally provided on the lead frame 20 through bonding wires 22; an encapsulant 23 is formed on the lead frame 20; and then the semiconductor package structure 2 is etched for a second time such that each of the contact pads 201 protrudes from the bottom of the semiconductor package structure 2 by about half of the thickness of the lead frame 20. Further, the contact pads 201 can be arranged in array.
However, although a certain gap is provided between the contact pads and the circuit board and array-arranged contact pads are provided, since long bonding wires are required to electrically connect the semiconductor chip to the contact pads located far away, it adversely affects the electrical performance of the package structure. Further, due to tangling of the bonding wires, it is difficult for the package structure to provide high density I/O connections.
Therefore, it is imperative to overcome the above drawbacks of the prior art.